Category: HIGHSPEED

• Eye Diagram Using LFSR

  Heya,

  Unfortunately I am back to school again, but I only have one hard class (designing op amp), and 2 garbage classes, so I probably will continue working on this.

  Last time, I managed to transmit signals over 1000 foot UTP cable. However, to check whether it was garbage signals or not we need to generate eye-diagram to analyze our signals. I had no luck creating appropriate eye-diagram due to the code I uploaded to the Arduino. I needed something that have separate clock and something random.

  Talking about random, I thought about linear–feedback shift register (LFSR). LFSR is a shift register and with a feedback of two or more “taps”. Based on the circuit schematic shown in Picture 1, I tapped bit 0 and 2. You can of course tap more than two, however, there are certain of pattern you need to follow (refer to Picture 2) that can be referred to the length of the loop.

  

  

  Moreover, LFSR would spit out pseudo-random numbers that I need for my eye-diagram testing. The previous set up with Arduino was bad because it spit out constant pattern that of course you can’t analyze whether your signal is bad or not.

  So, I built LFSR with d-flip flop (using TI SN74LS273N), and XOR gate ( HD74LS86 )

  

  Using the circuit set up from Picture 1 (a), I use function generator as a clock for the D-flip flop, and output it from pin #6 of the d-flip flop (since I’m only using 2 taps).

  anddddd there she is, the not so pretty eye-diagram (lol). But it’s a progress!

  

  

  

  October 6, 2019

  Circuit Analysis, Electrical Engineering, LFSR, RS485, Signal Integrity, XOR Gate

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• Why RS-485?

  Hello people!

  It’s been a while since my last post. I actually did a little summer activities (hiking, gardening, rearranging pantry, making soap etc). BUT I also managed to design the circuit schematic for my serial communication project.

  The schematic as shown in Figure 1 is very drafty. I was using Altium Designer for it, but since I am not making PCB at this moment, I thought this should be doable as my breadboarding reference. Again, this schematic is awful because you can’t really see the flow from the original to the isolation section. I will fix it later!

  

  Breadboarding part I: Look at those loops!

  

  Then I realized that those loops could introduce unwanted inductance, so I revised.

  

  As you can see, they look so much better! FLAT. You’d want them flat like that. It’s a tedious work, but I shall get used to it.

  For multigiga serial links (with increasing bitrates), it would suffer from signal distortions. While SerDes receiver designed to compensate those distortions, by creating a bigger eye opening (see: eye diagram) for reliable sampling, the bit rates also rising faster than Rx, PCB, and package HDI. This results in decreasing reachable total channel. RS-485 is a type of repeater that could restore the signals, hence RS-485 extending the channel reach.

  

  RS-485 use differential signaling over twisted pair, which is beneficial. We know from circuit theory, that differential signaling technique reduces electromagnetic interference (EMI) that could cause cross-talk. In addition, RS-485 also use 3-state logic (1, 0 and high Z) that allows individual transmitter to be deactivated.

  The schematic and circuit board above (see Figures 1,2,3), uses RS-485 as a repeater and it connected it to digital isolator to ensure the power-supply voltage to the MCU is compatible and DC-DC converter to rectify the whole process back to the DC.

  If you notice, the circuit diagram for DC-DC converter contains Inductor(L) and Capacitor (C). The LC circuit is a simple low pass filter to filter out unwanted signals that may present above the wanted pass band.

  So in theory, once we connect all of these out to the UTP cable, 50m cable should not signal faster than 2Mbit/s. We’ll see!

  Will keep you updated.

  Source: https://www.intel.com/content/www/us/en/io/serial-bus-white-paper.html

  August 25, 2019

  Electrical Engineering, repeater, RS485, Signal Integrity

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